CLUSTER HEAD ELECTION MECHANISM-BASED ON FUZZY LOGIC (CHEF) WITH TDMA IN WSN

Wireless sensor networks (WSN) are being used for huge range of applications where the traditional infrastructure based network is mostly infeasible. The most challenging aspect of WSN is that they are energy resource-constrained and that energy cannot be replenish. the wireless sensor network of power limited sensing devices called sensor deployed in a region to sense various types physical information from the environment, when these sensors sense and transmit data to other sensors present in the network, even the cluster head is elected according to check their residual energy considerable amount of energy will drain automatically to overcome this drawback by considering the protocol a fuzzy logic approach is used to elect the cluster head based on three descriptors-energy, centrality & distance and second CH is elected according to TDMA to overcome the data lost during energy drain occur in the CH .NS-2 simulation shows that proposed protocol provides higher energy efficiency. This paper proposes the mechanism or device is capable of utilizing its own system of control simply called as self-configurable clustering mechanism to detect the disordered CHs and replace them with other nodes. And results have been derived from simulator ns-2 to show the better performance

A MEMORY EFFICIENT HARDWARE BASED PATTERN MATCHING AND PROTEIN ALIGNMENT SCHEMES FOR HIGHLY COMPLEX DATABASES

Protein sequence alignment to find correlation between different species, or genetic mutations etc. is the most computational intensive task when performing protein comparison. To speed-up the alignment, Systolic Arrays (SAs) have been used. In order to avoid the internal-loop problem which reduces the performance, pipeline interleaving strategy has been presented. This strategy is applied to an SA for Smith Waterman (SW) algorithm which is an alignment algorithm to locally align two proteins. In the proposed system, the above methodology has been extended to implement a memory efficient FPGA-hardware based Network Intrusion Detection System (NIDS) to speed up network processing. The pattern matching in Intrusion Detection Systems (IDS) is done using SNORT to find the pattern of intrusions. A Finite State Machine (FSM) based Processing Elements (PE) unit to achieve minimum number of states for pattern matching and bit wise early intrusion detection to increase the throughput by pipelining is presented

ANDROID BASED HOME AUTOMATION AND ENERGY CONSERVATION

Wireless Sensor Network (WSN) consists of three main components: nodes, gateways, and software. The spatially distributed measurement nodes interface with sensors to monitor assets or their environment. In a WSN network the devices are connected to WSN nodes wherein the entire nodes uses Zigbee network to transfer the status of connected applications to a controller which controls the whole applications but the main drawback of Wireless sensor networks is its high interference, low coverage area and ability to control only low power devices. In order to overcome these drawbacks Android equipped devices are used to control the applications over GPRS network. Android equipped devices allow the user to control various applications over wireless networks. Being an open sourced platform it allows the user to design a custom module which controls the home applications by connecting the android equipped device and its corresponding home applications to an MCU wherein it uses relay circuits to connect the entire applications using GPRS network to connect the application controller and the android device. These devices can be used to control industrial applications, home applications like light, fan etc., and thereby conserving electricity

DESIGN OF LOW POWER CARRY SKIP ADDER USING DTCMOS

In the domain of VLSI design, the adders are always meant to be the most fundamental requirements for processors of high performance and other multicore devices. It is found that power dissipation is a major problem in the electronic devices. Power management integrated circuit (PMIC) is emphasized as battery-powered portable electronics such as smart phone are commonly used. In this paper we are designing a carry skip adder which consumes less power than the other conventional adders using dynamic threshold complementary metal oxide semiconductor (DTCMOS).Tthe circuit is designed using tanner EDA simulator of 32nm technology. Also the circuit is compared with the CMOS technology methods